1. Field of the Invention
The present invention relates to a clock-synchronized input circuit, which inputs data signals in synchronous with a clock, and semiconductor memory device that utilizes same.
2. Description of the Related Art
In semiconductor devices, which are supplied with command data, write data and addresses in synchronous with an external clock, for example, semiconductor memory device such as synchronous DRAM, clock-synchronized input circuits are provided to receive these data signals. Generally, this clock-synchronized input circuit samples supplied data signals via a differential circuit activated by an external clock, converts that sampled data signal to an internal CMOS level signal and holds it via a latch circuit. In this case, a specification requires the fact that a supplied data signal has a higher or lower voltage level than a reference voltage by a predetermined voltage, for example.
FIG. 9 is a circuit diagram depicting an example of such an input circuit. In this example, the input circuit comprises a sampling unit 22, which samples externally-supplied data signals IN by comparing them to a reference voltage Vref, a latch circuit 16 for amplifying and latching nodes n10, n12, at which the results of this sampling is generated, a level conversion unit 18, which converts the levels of those latched outputs n14, n16 to internal CMOS levels, and a hold circuit 21, which latches and holds those outputs n18, n20. Further, the sampling unit 22 is activated by a transistor 15, which conducts by virtue of pulses 23 generated by an external clock CLK, and the latch circuit 16 is activated by a transistor 17, which conducts by virtue of the external clock CLK H level.
By way of explaining in rough terms the operation of the input circuit depicted in FIG. 9, p-type transistors 10, 11 conduct by virtue of the L level of the clock CLK, and both nodes n10, n11 achieve an H level reset state. Then, when a data signal is supplied to input IN and the clock CLK simultaneously rises, a pulse generator 14 generates a pulse signal 23 in synchronous with the rising edge of the clock CLK, causing the transistor 15 to conduct. This activates a differential circuit comprising transistors 12, 13 with a common source. The data signal IN and a reference voltage Vref are applied to the gates of transistors 12 and 13, respectively. This data signal IN is supplied at a predetermined voltage that is higher or lower than the reference voltage Vref. Therefore, the differential amplification of the transistors 12, 13 causes one of the transistors to conduct, one of the nodes n10, n11, which were reset to H level, is driven to L level, and data signal IN sampling is performed.
The H and L levels of these nodes n10, n11 are further amplified by the latch circuit 16, and latched one time. The latch circuit 16 is also activated by a transistor 17 made conductive by the H level of the external clock CLK. Therefore, sampling operations are implemented by the sampling unit 22 and latch circuit 16 in synchronous with the clock CLK.
Latch circuit 16 outputs n14, n16 are each converted to internal COMS (CMOS) levels by a level converter 18. Then, the level-converted signals at nodes n18, n20 are held by a latch circuit 21 comprised of inverters 19, 20. The latch circuit 21 holds the data signals even after the external clock CLK changes into L level.
When a command signal is supplied as a data signal to the input circuit depicted in FIG. 9, inverted and non-inverted command signals are output to those outputs Outx, Outz. Also, when an address signal is supplied as a data signal, that address signal is output as inverted and non-inverted signals.
The above-described input circuit samples an externally-supplied data signal by comparing it with a reference voltage to determine if it is H level or L level, and holds that sampled data signal. However, the time required for data signal sampling differs according to the size of the margin of the supplied data signal relative to the reference voltage. As a result, the timing of the conversion of the input circuit outputs Outx, Outz also differs according to the above-mentioned margin.
For example, with a synchronous DRAM, a plurality of command signals are supplied in synchronous with the rising edge of an external clock CLK, and these command signals are sampled and held by the respective input circuits. Then, these sampled command signals are decoded by a command decoder, and a variety of internal operations are controlled.
FIG. 10 is a timing chart for explaining the problems that arise when a plurality of command signals /CS, /RAS, /CAS, /WE, CKE are supplied. In this example, a plurality of command signals /CS, /RAS, /CAS, /WE, CKE are supplied based on the timing of the rising edges clk1 and clk2 of an external clock CLK. Now, hypothetically, let us assume that, of these command signals, the level of the chip select signal /CS has a sufficiently large margin relative to the reference voltage Vref, and, similarly, the row address strobe signal /RAS also has a relatively large margin, but, the column address strobe signal /CAS possesses a small margin.
The L level of the signals /CS, /RAS, /CAS supplied on the bases of rising edge clk1 timing are sampled and held in the input circuit. As a result, as depicted in the figure, the latched signals 30, 31, 32 make the transition to L level accompanied by a predetermined delay time. This delay time is the input circuit's operation time. As a result, what was an inactive state during period 36, becomes an auto-refresh mode in period 38 due to a combination of L levels of command signals /CS, /RAS, /CAS. An auto-refresh mode raises a memory word line in accordance with an internally-generated address, amplifies via a sense amplifier memory data stored in a memory cell and carries out rewrite.
Next, let us assume that the chip select signal /CS is supplied at L level, the row address strobe signal /RAS is supplied at H level, and the column address strobe signal /CAS is supplied at H level all on the basis of the rising edge clk2 timing of the external clock CLK. As explained above, since the /RAS signal has a relatively large margin, input circuit operational delay time is short, but because the /CAS signal has a small margin relative to the reference voltage, the operational delay time required for the input circuit to detect the H level is long. Therefore, the sampled and latched signal 32 corresponding to the /CAS signal is delayed more than the sampled and latched signal 31 corresponding to the /RAS signal. With the differential circuit architecture of the sampling element 22 depicted in FIG. 9, the difference in these operational delays is especially large in the case of an H level data signal IN.
In period 39, when this skewing is generated, both the /CS signal and the /CAS signal temporarily become L level, and are decoded as a read mode. Despite the fact that a no operation mode command signal combination (NOP), wherein all the command signals are H level, except the /CS signal having L level, is supplied on the basis of external clock rising edge clk2 timing, an L level state is generated for both the /CS signal and the /CAS signal internally due to the dispersion of the input circuit delay times accompanying the dispersion of the respective command signal margins. This temporarily generates a read mode internally as shown in period 39.
In the read mode, the sense amplifier is connected to a data bus and data is read from an output circuit. Normally, the capacitance load of a data bus is large, so that the sense amplifier cannot drive the data bus until a predetermined amount of time has elapsed following the rising of the word line and the activation of the sense amplifier. Therefore, when a transition to the read mode occurs at an unanticipated timing, like during period 39, the sense amplifier state can break down, and rewrite data can be destroyed even in the auto-refresh mode.
Even with command signal combinations other than those described above, malfunctions can occur by the generation of skewing in internally-latched signals from the differences in internal circuit delay times. Furthermore, this skewing is not limited to command signals, and decode circuit malfunctions can also be brought about by the occurrence of internal skewing with relation to a plurality of address signals.